It has been proposed to use programmable resistive elements in memory cells to provide non-volatile data storage. Such resistive elements are programmable to adopt one of a plurality of different resistive states. The programmed resistive state is maintained when the supply voltage of the memory cell is disconnected, and thus data can be stored in a non-volatile fashion.
Various types of resistive elements have been proposed, some of which are capable of being programmed by the direction and/or level of the current which is passed through them. Examples of such current-programmable resistive elements include OxRAM (Oxide Random Access Memory), PC-RAM (Phase Change Random Access Memory) and MRAM (magnetic RAM) using for example STT (spin-transfer torque) technology.
In order to provide a compact memory array, it has been proposed to incorporate non-volatile memory cells in a cross-point memory array architecture. In such an array, memory cells are arranged in rows and columns, each row having an associated row line, and each column having an associated column line. Each memory cell comprises a programmable resistive element coupled between a corresponding row line and a corresponding column line. Thus by applying particular voltage levels to the column and row lines, a given memory cell in the array can be selected for a read or write operation.
Depending on the particular technology of the non-volatile programmable resistive element, the level of the programming current used during the programming operation may affect a certain property of the programmed resistive state, such as the programmed resistance and/or the data retention duration.
For example, in the case of an OxRAM memory cell, when passing from the high resistive state to the low resistive state, the programming current will rise rapidly, and the level reached by the programming current will determine the programmed resistance level of the cell. Therefore, in order to program a particular desired resistance, the current should be limited during the programming operation.
However, a difficulty in cross-point memory arrays is that, while a given memory cell is being programmed, a certain amount of the current driven into the array will be lost via current leakage through non-selected memory cells. Such current paths are known in the art as sneak paths. The amount of current conducted via sneak paths will depend on various factors, such as the resistive states of the non-selected memory cells, the position of the selected memory cell in the array, the operating conditions, the age of the device and the performance of other components in each memory cell. There is a technical problem in adequately compensating for such leakage currents.
There is thus a need in the art for a circuit and method providing effective current limitation during programming operations in a non-volatile cross-point memory array.